include, but are not limited to the following High level architecture specification analysis interactive authoring and review. Micro architecture development and documentation. High quality, high performance Verilog/SystemVerilog RTL implementation based on a design specification may also include areas such as asynchronous clock domain crossings, multiple power domains, lo

include, but are not limited to the following High level architecture specification analysis interactive authoring and review. Micro architecture development and documentation. High quality, high performance Verilog/SystemVerilog RTL implementation based on a design specification may also include areas such as asynchronous clock domain crossings, multiple power domains, lo

Engineer would be responsible for developing functional and architectural models for PCIe/CXL Switch and RAID Controller products Perform technical investigations and/or debug within our current solutions in order to optimize model performance, evaluate future modelling enhancements. Present on Modelling Architecture related topics to executive management in a clear and c

Actively contributes to defining vision for the Architecture & Engineering function Advocates and encourages innovation, creative thought, and new ideas and/or solutions Contributes to publications and community events Delivering workshops with customers and PSO consultants on or off customer premises to thoroughly capture requirements. Analyzing requirements and designin